\UART_2:BUART:tx_state_2\/q |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
44.853 MHz |
22.295 |
1061.038 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell22 |
U(1,1) |
1 |
\UART_2:BUART:tx_state_2\ |
\UART_2:BUART:tx_state_2\/clock_0 |
\UART_2:BUART:tx_state_2\/q |
1.250 |
Route |
|
1 |
\UART_2:BUART:tx_state_2\ |
\UART_2:BUART:tx_state_2\/q |
\UART_2:BUART:counter_load_not\/main_2 |
3.883 |
macrocell2 |
U(1,1) |
1 |
\UART_2:BUART:counter_load_not\ |
\UART_2:BUART:counter_load_not\/main_2 |
\UART_2:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_2:BUART:counter_load_not\ |
\UART_2:BUART:counter_load_not\/q |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.292 |
datapathcell3 |
U(1,1) |
1 |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
11.520 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_2:BUART:tx_state_0\/q |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
45.844 MHz |
21.813 |
1061.520 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell20 |
U(0,1) |
1 |
\UART_2:BUART:tx_state_0\ |
\UART_2:BUART:tx_state_0\/clock_0 |
\UART_2:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART_2:BUART:tx_state_0\ |
\UART_2:BUART:tx_state_0\/q |
\UART_2:BUART:counter_load_not\/main_1 |
3.401 |
macrocell2 |
U(1,1) |
1 |
\UART_2:BUART:counter_load_not\ |
\UART_2:BUART:counter_load_not\/main_1 |
\UART_2:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_2:BUART:counter_load_not\ |
\UART_2:BUART:counter_load_not\/q |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.292 |
datapathcell3 |
U(1,1) |
1 |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
11.520 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_2:BUART:tx_state_1\/q |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
46.200 MHz |
21.645 |
1061.688 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell21 |
U(1,1) |
1 |
\UART_2:BUART:tx_state_1\ |
\UART_2:BUART:tx_state_1\/clock_0 |
\UART_2:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART_2:BUART:tx_state_1\ |
\UART_2:BUART:tx_state_1\/q |
\UART_2:BUART:counter_load_not\/main_0 |
3.233 |
macrocell2 |
U(1,1) |
1 |
\UART_2:BUART:counter_load_not\ |
\UART_2:BUART:counter_load_not\/main_0 |
\UART_2:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_2:BUART:counter_load_not\ |
\UART_2:BUART:counter_load_not\/q |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.292 |
datapathcell3 |
U(1,1) |
1 |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
11.520 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_2:BUART:tx_bitclk\/q |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
46.509 MHz |
21.501 |
1061.832 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell18 |
U(0,1) |
1 |
\UART_2:BUART:tx_bitclk\ |
\UART_2:BUART:tx_bitclk\/clock_0 |
\UART_2:BUART:tx_bitclk\/q |
1.250 |
Route |
|
1 |
\UART_2:BUART:tx_bitclk\ |
\UART_2:BUART:tx_bitclk\/q |
\UART_2:BUART:counter_load_not\/main_3 |
3.089 |
macrocell2 |
U(1,1) |
1 |
\UART_2:BUART:counter_load_not\ |
\UART_2:BUART:counter_load_not\/main_3 |
\UART_2:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_2:BUART:counter_load_not\ |
\UART_2:BUART:counter_load_not\/q |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.292 |
datapathcell3 |
U(1,1) |
1 |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
11.520 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb |
\UART_2:BUART:sTX:TxShifter:u0\/cs_addr_0 |
50.218 MHz |
19.913 |
1063.420 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell3 |
U(1,1) |
1 |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/clock |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb |
5.680 |
Route |
|
1 |
\UART_2:BUART:tx_bitclk_dp\ |
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb |
\UART_2:BUART:tx_bitclk_enable_pre\/main_0 |
2.301 |
macrocell19 |
U(0,1) |
1 |
\UART_2:BUART:tx_bitclk_enable_pre\ |
\UART_2:BUART:tx_bitclk_enable_pre\/main_0 |
\UART_2:BUART:tx_bitclk_enable_pre\/q |
3.350 |
Route |
|
1 |
\UART_2:BUART:tx_bitclk_enable_pre\ |
\UART_2:BUART:tx_bitclk_enable_pre\/q |
\UART_2:BUART:sTX:TxShifter:u0\/cs_addr_0 |
2.292 |
datapathcell2 |
U(0,1) |
1 |
\UART_2:BUART:sTX:TxShifter:u0\ |
|
SETUP |
6.290 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_2:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
\UART_2:BUART:sTX:TxSts\/status_0 |
59.182 MHz |
16.897 |
1066.436 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell2 |
U(0,1) |
1 |
\UART_2:BUART:sTX:TxShifter:u0\ |
\UART_2:BUART:sTX:TxShifter:u0\/clock |
\UART_2:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
5.280 |
Route |
|
1 |
\UART_2:BUART:tx_fifo_empty\ |
\UART_2:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
\UART_2:BUART:tx_status_0\/main_2 |
4.374 |
macrocell23 |
U(0,1) |
1 |
\UART_2:BUART:tx_status_0\ |
\UART_2:BUART:tx_status_0\/main_2 |
\UART_2:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART_2:BUART:tx_status_0\ |
\UART_2:BUART:tx_status_0\/q |
\UART_2:BUART:sTX:TxSts\/status_0 |
2.323 |
statusicell2 |
U(0,1) |
1 |
\UART_2:BUART:sTX:TxSts\ |
|
SETUP |
1.570 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_2:BUART:rx_state_3\/q |
\UART_2:BUART:sRX:RxBitCounter\/load |
65.130 MHz |
15.354 |
1067.979 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell13 |
U(0,0) |
1 |
\UART_2:BUART:rx_state_3\ |
\UART_2:BUART:rx_state_3\/clock_0 |
\UART_2:BUART:rx_state_3\/q |
1.250 |
Route |
|
1 |
\UART_2:BUART:rx_state_3\ |
\UART_2:BUART:rx_state_3\/q |
\UART_2:BUART:rx_counter_load\/main_2 |
4.279 |
macrocell7 |
U(0,0) |
1 |
\UART_2:BUART:rx_counter_load\ |
\UART_2:BUART:rx_counter_load\/main_2 |
\UART_2:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_2:BUART:rx_counter_load\ |
\UART_2:BUART:rx_counter_load\/q |
\UART_2:BUART:sRX:RxBitCounter\/load |
2.255 |
count7cell |
U(0,0) |
1 |
\UART_2:BUART:sRX:RxBitCounter\ |
|
SETUP |
4.220 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_2:BUART:pollcount_1\/q |
\UART_2:BUART:sRX:RxShifter:u0\/route_si |
66.751 MHz |
14.981 |
1068.352 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell4 |
U(0,1) |
1 |
\UART_2:BUART:pollcount_1\ |
\UART_2:BUART:pollcount_1\/clock_0 |
\UART_2:BUART:pollcount_1\/q |
1.250 |
Route |
|
1 |
\UART_2:BUART:pollcount_1\ |
\UART_2:BUART:pollcount_1\/q |
\UART_2:BUART:rx_postpoll\/main_0 |
2.307 |
macrocell10 |
U(0,1) |
1 |
\UART_2:BUART:rx_postpoll\ |
\UART_2:BUART:rx_postpoll\/main_0 |
\UART_2:BUART:rx_postpoll\/q |
3.350 |
Route |
|
1 |
\UART_2:BUART:rx_postpoll\ |
\UART_2:BUART:rx_postpoll\/q |
\UART_2:BUART:sRX:RxShifter:u0\/route_si |
2.864 |
datapathcell1 |
U(0,0) |
1 |
\UART_2:BUART:sRX:RxShifter:u0\ |
|
SETUP |
5.210 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_2:BUART:pollcount_0\/q |
\UART_2:BUART:sRX:RxShifter:u0\/route_si |
66.774 MHz |
14.976 |
1068.357 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell3 |
U(0,1) |
1 |
\UART_2:BUART:pollcount_0\ |
\UART_2:BUART:pollcount_0\/clock_0 |
\UART_2:BUART:pollcount_0\/q |
1.250 |
Route |
|
1 |
\UART_2:BUART:pollcount_0\ |
\UART_2:BUART:pollcount_0\/q |
\UART_2:BUART:rx_postpoll\/main_2 |
2.302 |
macrocell10 |
U(0,1) |
1 |
\UART_2:BUART:rx_postpoll\ |
\UART_2:BUART:rx_postpoll\/main_2 |
\UART_2:BUART:rx_postpoll\/q |
3.350 |
Route |
|
1 |
\UART_2:BUART:rx_postpoll\ |
\UART_2:BUART:rx_postpoll\/q |
\UART_2:BUART:sRX:RxShifter:u0\/route_si |
2.864 |
datapathcell1 |
U(0,0) |
1 |
\UART_2:BUART:sRX:RxShifter:u0\ |
|
SETUP |
5.210 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_2:BUART:rx_state_0\/q |
\UART_2:BUART:sRX:RxBitCounter\/load |
67.404 MHz |
14.836 |
1068.497 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell11 |
U(0,0) |
1 |
\UART_2:BUART:rx_state_0\ |
\UART_2:BUART:rx_state_0\/clock_0 |
\UART_2:BUART:rx_state_0\/q |
1.250 |
Route |
|
1 |
\UART_2:BUART:rx_state_0\ |
\UART_2:BUART:rx_state_0\/q |
\UART_2:BUART:rx_counter_load\/main_1 |
3.761 |
macrocell7 |
U(0,0) |
1 |
\UART_2:BUART:rx_counter_load\ |
\UART_2:BUART:rx_counter_load\/main_1 |
\UART_2:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_2:BUART:rx_counter_load\ |
\UART_2:BUART:rx_counter_load\/q |
\UART_2:BUART:sRX:RxBitCounter\/load |
2.255 |
count7cell |
U(0,0) |
1 |
\UART_2:BUART:sRX:RxBitCounter\ |
|
SETUP |
4.220 |
Clock |
|
|
|
|
Skew |
0.000 |
|