Project : | UART_Bootloader |
Build Time : | 01/22/15 14:16:14 |
Device : | CY8C4245AXI-483 |
Temperature : | -40C - 85C |
VDDA : | 5.00 |
VDDD : | 5.00 |
Voltage : | 5 |
Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation |
---|---|---|---|---|---|
Clock(FFB) | Clock(FFB) | 20.000 kHz | 20.000 kHz | N/A | |
CyHFCLK | CyHFCLK | 24.000 MHz | 24.000 MHz | N/A | |
UART_SCBCLK | CyHFCLK | 1.412 MHz | 1.412 MHz | N/A | |
Clock | CyHFCLK | 20.000 kHz | 20.000 kHz | N/A | |
CyILO | CyILO | 32.000 kHz | 32.000 kHz | N/A | |
CyIMO | CyIMO | 24.000 MHz | 24.000 MHz | N/A | |
CyLFCLK | CyLFCLK | 32.000 kHz | 32.000 kHz | N/A | |
CyRouted1 | CyRouted1 | 24.000 MHz | 24.000 MHz | N/A | |
CySYSCLK | CySYSCLK | 24.000 MHz | 24.000 MHz | N/A | |
UART_SCBCLK(FFB) | UART_SCBCLK(FFB) | 1.412 MHz | 1.412 MHz | N/A |
Source | Destination | Delay (ns) | ||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
\PWM:cy_m0s8_tcpwm_1\/line_out | P1_6(0)_PAD | 21.115 | ||||||||||||||||||||||||||||||||||||||||||
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