Static Timing Analysis

Project : GeigerWithMotor
Build Time : 02/06/15 21:08:11
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 5.00
VDDD : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz 46.479 MHz
UART_1_SCBCLK CyHFCLK 923.077 kHz 923.077 kHz N/A
Clock_1 CyHFCLK 923.077 kHz 923.077 kHz 44.853 MHz
I2C_1_SCBCLK CyHFCLK 1.600 MHz 1.600 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
I2C_1_SCBCLK(FFB) I2C_1_SCBCLK(FFB) 1.600 MHz 1.600 MHz N/A
UART_1_SCBCLK(FFB) UART_1_SCBCLK(FFB) 923.077 kHz 923.077 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_2:BUART:tx_state_2\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.853 MHz 22.295 1061.038
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,1) 1 \UART_2:BUART:tx_state_2\ \UART_2:BUART:tx_state_2\/clock_0 \UART_2:BUART:tx_state_2\/q 1.250
Route 1 \UART_2:BUART:tx_state_2\ \UART_2:BUART:tx_state_2\/q \UART_2:BUART:counter_load_not\/main_2 3.883
macrocell2 U(1,1) 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/main_2 \UART_2:BUART:counter_load_not\/q 3.350
Route 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell3 U(1,1) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_2:BUART:tx_state_0\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.844 MHz 21.813 1061.520
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,1) 1 \UART_2:BUART:tx_state_0\ \UART_2:BUART:tx_state_0\/clock_0 \UART_2:BUART:tx_state_0\/q 1.250
Route 1 \UART_2:BUART:tx_state_0\ \UART_2:BUART:tx_state_0\/q \UART_2:BUART:counter_load_not\/main_1 3.401
macrocell2 U(1,1) 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/main_1 \UART_2:BUART:counter_load_not\/q 3.350
Route 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell3 U(1,1) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_2:BUART:tx_state_1\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.200 MHz 21.645 1061.688
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,1) 1 \UART_2:BUART:tx_state_1\ \UART_2:BUART:tx_state_1\/clock_0 \UART_2:BUART:tx_state_1\/q 1.250
Route 1 \UART_2:BUART:tx_state_1\ \UART_2:BUART:tx_state_1\/q \UART_2:BUART:counter_load_not\/main_0 3.233
macrocell2 U(1,1) 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/main_0 \UART_2:BUART:counter_load_not\/q 3.350
Route 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell3 U(1,1) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_2:BUART:tx_bitclk\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.509 MHz 21.501 1061.832
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \UART_2:BUART:tx_bitclk\ \UART_2:BUART:tx_bitclk\/clock_0 \UART_2:BUART:tx_bitclk\/q 1.250
Route 1 \UART_2:BUART:tx_bitclk\ \UART_2:BUART:tx_bitclk\/q \UART_2:BUART:counter_load_not\/main_3 3.089
macrocell2 U(1,1) 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/main_3 \UART_2:BUART:counter_load_not\/q 3.350
Route 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell3 U(1,1) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_2:BUART:sTX:TxShifter:u0\/cs_addr_0 50.218 MHz 19.913 1063.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,1) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART_2:BUART:tx_bitclk_dp\ \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_2:BUART:tx_bitclk_enable_pre\/main_0 2.301
macrocell19 U(0,1) 1 \UART_2:BUART:tx_bitclk_enable_pre\ \UART_2:BUART:tx_bitclk_enable_pre\/main_0 \UART_2:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_2:BUART:tx_bitclk_enable_pre\ \UART_2:BUART:tx_bitclk_enable_pre\/q \UART_2:BUART:sTX:TxShifter:u0\/cs_addr_0 2.292
datapathcell2 U(0,1) 1 \UART_2:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART_2:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_2:BUART:sTX:TxSts\/status_0 59.182 MHz 16.897 1066.436
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART_2:BUART:sTX:TxShifter:u0\ \UART_2:BUART:sTX:TxShifter:u0\/clock \UART_2:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_2:BUART:tx_fifo_empty\ \UART_2:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_2:BUART:tx_status_0\/main_2 4.374
macrocell23 U(0,1) 1 \UART_2:BUART:tx_status_0\ \UART_2:BUART:tx_status_0\/main_2 \UART_2:BUART:tx_status_0\/q 3.350
Route 1 \UART_2:BUART:tx_status_0\ \UART_2:BUART:tx_status_0\/q \UART_2:BUART:sTX:TxSts\/status_0 2.323
statusicell2 U(0,1) 1 \UART_2:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_2:BUART:rx_state_3\/q \UART_2:BUART:sRX:RxBitCounter\/load 65.130 MHz 15.354 1067.979
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(0,0) 1 \UART_2:BUART:rx_state_3\ \UART_2:BUART:rx_state_3\/clock_0 \UART_2:BUART:rx_state_3\/q 1.250
Route 1 \UART_2:BUART:rx_state_3\ \UART_2:BUART:rx_state_3\/q \UART_2:BUART:rx_counter_load\/main_2 4.279
macrocell7 U(0,0) 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/main_2 \UART_2:BUART:rx_counter_load\/q 3.350
Route 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/q \UART_2:BUART:sRX:RxBitCounter\/load 2.255
count7cell U(0,0) 1 \UART_2:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART_2:BUART:pollcount_1\/q \UART_2:BUART:sRX:RxShifter:u0\/route_si 66.751 MHz 14.981 1068.352
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,1) 1 \UART_2:BUART:pollcount_1\ \UART_2:BUART:pollcount_1\/clock_0 \UART_2:BUART:pollcount_1\/q 1.250
Route 1 \UART_2:BUART:pollcount_1\ \UART_2:BUART:pollcount_1\/q \UART_2:BUART:rx_postpoll\/main_0 2.307
macrocell10 U(0,1) 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/main_0 \UART_2:BUART:rx_postpoll\/q 3.350
Route 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/q \UART_2:BUART:sRX:RxShifter:u0\/route_si 2.864
datapathcell1 U(0,0) 1 \UART_2:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART_2:BUART:pollcount_0\/q \UART_2:BUART:sRX:RxShifter:u0\/route_si 66.774 MHz 14.976 1068.357
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,1) 1 \UART_2:BUART:pollcount_0\ \UART_2:BUART:pollcount_0\/clock_0 \UART_2:BUART:pollcount_0\/q 1.250
Route 1 \UART_2:BUART:pollcount_0\ \UART_2:BUART:pollcount_0\/q \UART_2:BUART:rx_postpoll\/main_2 2.302
macrocell10 U(0,1) 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/main_2 \UART_2:BUART:rx_postpoll\/q 3.350
Route 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/q \UART_2:BUART:sRX:RxShifter:u0\/route_si 2.864
datapathcell1 U(0,0) 1 \UART_2:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART_2:BUART:rx_state_0\/q \UART_2:BUART:sRX:RxBitCounter\/load 67.404 MHz 14.836 1068.497
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 \UART_2:BUART:rx_state_0\ \UART_2:BUART:rx_state_0\/clock_0 \UART_2:BUART:rx_state_0\/q 1.250
Route 1 \UART_2:BUART:rx_state_0\ \UART_2:BUART:rx_state_0\/q \UART_2:BUART:rx_counter_load\/main_1 3.761
macrocell7 U(0,0) 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/main_1 \UART_2:BUART:rx_counter_load\/q 3.350
Route 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/q \UART_2:BUART:sRX:RxBitCounter\/load 2.255
count7cell U(0,0) 1 \UART_2:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_2:BUART:sRX:RxShifter:u0\/route_si 46.479 MHz 21.515 20.152
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_postpoll\/main_1 6.044
macrocell10 U(0,1) 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/main_1 \UART_2:BUART:rx_postpoll\/q 3.350
Route 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/q \UART_2:BUART:sRX:RxShifter:u0\/route_si 2.864
datapathcell1 U(0,0) 1 \UART_2:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:pollcount_0\/main_2 73.524 MHz 13.601 28.066
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:pollcount_0\/main_2 6.044
macrocell3 U(0,1) 1 \UART_2:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:pollcount_1\/main_3 73.524 MHz 13.601 28.066
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:pollcount_1\/main_3 6.044
macrocell4 U(0,1) 1 \UART_2:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_last\/main_0 75.844 MHz 13.185 28.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_last\/main_0 5.628
macrocell8 U(1,0) 1 \UART_2:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_state_0\/main_9 75.844 MHz 13.185 28.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_state_0\/main_9 5.628
macrocell11 U(0,0) 1 \UART_2:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_status_3\/main_6 75.844 MHz 13.185 28.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_status_3\/main_6 5.628
macrocell15 U(0,0) 1 \UART_2:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_state_2\/main_8 75.896 MHz 13.176 28.491
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_state_2\/main_8 5.619
macrocell12 U(0,0) 1 \UART_2:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\UART_2:BUART:rx_status_3\/q \UART_2:BUART:sRX:RxSts\/status_3 1.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,0) 1 \UART_2:BUART:rx_status_3\ \UART_2:BUART:rx_status_3\/clock_0 \UART_2:BUART:rx_status_3\/q 1.250
Route 1 \UART_2:BUART:rx_status_3\ \UART_2:BUART:rx_status_3\/q \UART_2:BUART:sRX:RxSts\/status_3 2.252
statusicell1 U(1,0) 1 \UART_2:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_2:BUART:rx_last\/q \UART_2:BUART:rx_state_2\/main_9 3.487
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,0) 1 \UART_2:BUART:rx_last\ \UART_2:BUART:rx_last\/clock_0 \UART_2:BUART:rx_last\/q 1.250
Route 1 \UART_2:BUART:rx_last\ \UART_2:BUART:rx_last\/q \UART_2:BUART:rx_state_2\/main_9 2.237
macrocell12 U(0,0) 1 \UART_2:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:pollcount_0\/q \UART_2:BUART:pollcount_0\/main_3 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,1) 1 \UART_2:BUART:pollcount_0\ \UART_2:BUART:pollcount_0\/clock_0 \UART_2:BUART:pollcount_0\/q 1.250
macrocell3 U(0,1) 1 \UART_2:BUART:pollcount_0\ \UART_2:BUART:pollcount_0\/q \UART_2:BUART:pollcount_0\/main_3 2.302
macrocell3 U(0,1) 1 \UART_2:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:pollcount_0\/q \UART_2:BUART:pollcount_1\/main_4 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,1) 1 \UART_2:BUART:pollcount_0\ \UART_2:BUART:pollcount_0\/clock_0 \UART_2:BUART:pollcount_0\/q 1.250
Route 1 \UART_2:BUART:pollcount_0\ \UART_2:BUART:pollcount_0\/q \UART_2:BUART:pollcount_1\/main_4 2.302
macrocell4 U(0,1) 1 \UART_2:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:txn\/q \UART_2:BUART:txn\/main_0 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,1) 1 \UART_2:BUART:txn\ \UART_2:BUART:txn\/clock_0 \UART_2:BUART:txn\/q 1.250
macrocell25 U(1,1) 1 \UART_2:BUART:txn\ \UART_2:BUART:txn\/q \UART_2:BUART:txn\/main_0 2.306
macrocell25 U(1,1) 1 \UART_2:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:pollcount_1\/q \UART_2:BUART:pollcount_1\/main_2 3.557
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,1) 1 \UART_2:BUART:pollcount_1\ \UART_2:BUART:pollcount_1\/clock_0 \UART_2:BUART:pollcount_1\/q 1.250
macrocell4 U(0,1) 1 \UART_2:BUART:pollcount_1\ \UART_2:BUART:pollcount_1\/q \UART_2:BUART:pollcount_1\/main_2 2.307
macrocell4 U(0,1) 1 \UART_2:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_load_fifo\/main_4 3.773
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,0) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/clock_0 \UART_2:BUART:rx_state_2\/q 1.250
Route 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_load_fifo\/main_4 2.523
macrocell9 U(0,0) 1 \UART_2:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_0\/main_4 3.773
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,0) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/clock_0 \UART_2:BUART:rx_state_2\/q 1.250
Route 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_0\/main_4 2.523
macrocell11 U(0,0) 1 \UART_2:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_2\/main_4 3.773
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,0) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/clock_0 \UART_2:BUART:rx_state_2\/q 1.250
macrocell12 U(0,0) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_2\/main_4 2.523
macrocell12 U(0,0) 1 \UART_2:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_3\/main_4 3.773
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,0) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/clock_0 \UART_2:BUART:rx_state_2\/q 1.250
Route 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_3\/main_4 2.523
macrocell13 U(0,0) 1 \UART_2:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_2:BUART:rx_state_2\/main_8 8.359
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_state_2\/main_8 5.619
macrocell12 U(0,0) 1 \UART_2:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_last\/main_0 8.368
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_last\/main_0 5.628
macrocell8 U(1,0) 1 \UART_2:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_state_0\/main_9 8.368
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_state_0\/main_9 5.628
macrocell11 U(0,0) 1 \UART_2:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_status_3\/main_6 8.368
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_status_3\/main_6 5.628
macrocell15 U(0,0) 1 \UART_2:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:pollcount_0\/main_2 8.784
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:pollcount_0\/main_2 6.044
macrocell3 U(0,1) 1 \UART_2:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:pollcount_1\/main_3 8.784
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:pollcount_1\/main_3 6.044
macrocell4 U(0,1) 1 \UART_2:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:sRX:RxShifter:u0\/route_si 14.998
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_postpoll\/main_1 6.044
macrocell10 U(0,1) 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/main_1 \UART_2:BUART:rx_postpoll\/q 3.350
Route 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/q \UART_2:BUART:sRX:RxShifter:u0\/route_si 2.864
datapathcell1 U(0,0) 1 \UART_2:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
\UART_2:BUART:txn\/q Tx_1(0)_PAD 29.628
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,1) 1 \UART_2:BUART:txn\ \UART_2:BUART:txn\/clock_0 \UART_2:BUART:txn\/q 1.250
Route 1 \UART_2:BUART:txn\ \UART_2:BUART:txn\/q Net_336/main_0 3.184
macrocell1 U(1,0) 1 Net_336 Net_336/main_0 Net_336/q 3.350
Route 1 Net_336 Net_336/q Tx_1(0)/pin_input 5.364
iocell5 P1[5] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.480
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000