Static Timing Analysis

Project : FreeRTOSDemo
Build Time : 01/22/15 15:22:25
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz 63.420 MHz
Clock_1 CyHFCLK 923.077 kHz 923.077 kHz 44.322 MHz
UART_1_SCBCLK CyHFCLK 923.077 kHz 923.077 kHz N/A
SCB_1_SCBCLK CyHFCLK 1.600 MHz 1.600 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
SCB_1_SCBCLK(FFB) SCB_1_SCBCLK(FFB) 1.600 MHz 1.600 MHz N/A
UART_1_SCBCLK(FFB) UART_1_SCBCLK(FFB) 923.077 kHz 923.077 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_2:BUART:tx_bitclk\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.322 MHz 22.562 1060.771
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,1) 1 \UART_2:BUART:tx_bitclk\ \UART_2:BUART:tx_bitclk\/clock_0 \UART_2:BUART:tx_bitclk\/q 1.250
Route 1 \UART_2:BUART:tx_bitclk\ \UART_2:BUART:tx_bitclk\/q \UART_2:BUART:counter_load_not\/main_3 4.150
macrocell2 U(0,1) 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/main_3 \UART_2:BUART:counter_load_not\/q 3.350
Route 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell3 U(0,1) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_2:BUART:tx_state_1\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.435 MHz 22.505 1060.828
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \UART_2:BUART:tx_state_1\ \UART_2:BUART:tx_state_1\/clock_0 \UART_2:BUART:tx_state_1\/q 1.250
Route 1 \UART_2:BUART:tx_state_1\ \UART_2:BUART:tx_state_1\/q \UART_2:BUART:counter_load_not\/main_0 4.093
macrocell2 U(0,1) 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/main_0 \UART_2:BUART:counter_load_not\/q 3.350
Route 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell3 U(0,1) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_2:BUART:tx_state_0\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.535 MHz 21.489 1061.844
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,1) 1 \UART_2:BUART:tx_state_0\ \UART_2:BUART:tx_state_0\/clock_0 \UART_2:BUART:tx_state_0\/q 1.250
Route 1 \UART_2:BUART:tx_state_0\ \UART_2:BUART:tx_state_0\/q \UART_2:BUART:counter_load_not\/main_1 3.077
macrocell2 U(0,1) 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/main_1 \UART_2:BUART:counter_load_not\/q 3.350
Route 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell3 U(0,1) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_2:BUART:tx_state_2\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.538 MHz 21.488 1061.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,1) 1 \UART_2:BUART:tx_state_2\ \UART_2:BUART:tx_state_2\/clock_0 \UART_2:BUART:tx_state_2\/q 1.250
Route 1 \UART_2:BUART:tx_state_2\ \UART_2:BUART:tx_state_2\/q \UART_2:BUART:counter_load_not\/main_2 3.076
macrocell2 U(0,1) 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/main_2 \UART_2:BUART:counter_load_not\/q 3.350
Route 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell3 U(0,1) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_2:BUART:sTX:TxShifter:u0\/cs_addr_0 48.766 MHz 20.506 1062.827
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART_2:BUART:tx_bitclk_dp\ \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_2:BUART:tx_bitclk_enable_pre\/main_0 2.302
macrocell16 U(0,1) 1 \UART_2:BUART:tx_bitclk_enable_pre\ \UART_2:BUART:tx_bitclk_enable_pre\/main_0 \UART_2:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_2:BUART:tx_bitclk_enable_pre\ \UART_2:BUART:tx_bitclk_enable_pre\/q \UART_2:BUART:sTX:TxShifter:u0\/cs_addr_0 2.884
datapathcell2 U(0,0) 1 \UART_2:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART_2:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_2:BUART:sRX:RxSts\/status_4 60.010 MHz 16.664 1066.669
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \UART_2:BUART:sRX:RxShifter:u0\ \UART_2:BUART:sRX:RxShifter:u0\/clock \UART_2:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_2:BUART:rx_fifofull\ \UART_2:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_2:BUART:rx_status_4\/main_1 2.292
macrocell13 U(1,1) 1 \UART_2:BUART:rx_status_4\ \UART_2:BUART:rx_status_4\/main_1 \UART_2:BUART:rx_status_4\/q 3.350
Route 1 \UART_2:BUART:rx_status_4\ \UART_2:BUART:rx_status_4\/q \UART_2:BUART:sRX:RxSts\/status_4 4.172
statusicell1 U(1,1) 1 \UART_2:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART_2:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_2:BUART:sTX:TxSts\/status_0 62.449 MHz 16.013 1067.320
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART_2:BUART:sTX:TxShifter:u0\ \UART_2:BUART:sTX:TxShifter:u0\/clock \UART_2:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_2:BUART:tx_fifo_empty\ \UART_2:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_2:BUART:tx_status_0\/main_2 3.490
macrocell20 U(0,1) 1 \UART_2:BUART:tx_status_0\ \UART_2:BUART:tx_status_0\/main_2 \UART_2:BUART:tx_status_0\/q 3.350
Route 1 \UART_2:BUART:tx_status_0\ \UART_2:BUART:tx_status_0\/q \UART_2:BUART:sTX:TxSts\/status_0 2.323
statusicell2 U(0,1) 1 \UART_2:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_2:BUART:rx_address_detected\/q \UART_2:BUART:sRX:RxBitCounter\/load 68.766 MHz 14.542 1068.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,0) 1 \UART_2:BUART:rx_address_detected\ \UART_2:BUART:rx_address_detected\/clock_0 \UART_2:BUART:rx_address_detected\/q 1.250
Route 1 \UART_2:BUART:rx_address_detected\ \UART_2:BUART:rx_address_detected\/q \UART_2:BUART:rx_counter_load\/main_0 3.472
macrocell5 U(0,0) 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/main_0 \UART_2:BUART:rx_counter_load\/q 3.350
Route 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/q \UART_2:BUART:sRX:RxBitCounter\/load 2.250
count7cell U(0,0) 1 \UART_2:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART_2:BUART:rx_state_0\/q \UART_2:BUART:sRX:RxBitCounter\/load 68.923 MHz 14.509 1068.824
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,0) 1 \UART_2:BUART:rx_state_0\ \UART_2:BUART:rx_state_0\/clock_0 \UART_2:BUART:rx_state_0\/q 1.250
Route 1 \UART_2:BUART:rx_state_0\ \UART_2:BUART:rx_state_0\/q \UART_2:BUART:rx_counter_load\/main_1 3.439
macrocell5 U(0,0) 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/main_1 \UART_2:BUART:rx_counter_load\/q 3.350
Route 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/q \UART_2:BUART:sRX:RxBitCounter\/load 2.250
count7cell U(0,0) 1 \UART_2:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART_2:BUART:rx_load_fifo\/q \UART_2:BUART:sRX:RxSts\/status_4 69.832 MHz 14.320 1069.013
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,0) 1 \UART_2:BUART:rx_load_fifo\ \UART_2:BUART:rx_load_fifo\/clock_0 \UART_2:BUART:rx_load_fifo\/q 1.250
Route 1 \UART_2:BUART:rx_load_fifo\ \UART_2:BUART:rx_load_fifo\/q \UART_2:BUART:rx_status_4\/main_0 3.978
macrocell13 U(1,1) 1 \UART_2:BUART:rx_status_4\ \UART_2:BUART:rx_status_4\/main_0 \UART_2:BUART:rx_status_4\/q 3.350
Route 1 \UART_2:BUART:rx_status_4\ \UART_2:BUART:rx_status_4\/q \UART_2:BUART:sRX:RxSts\/status_4 4.172
statusicell1 U(1,1) 1 \UART_2:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_2:BUART:sRX:RxShifter:u0\/route_si 63.420 MHz 15.768 25.899
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:sRX:RxShifter:u0\/route_si 6.511
datapathcell1 U(1,1) 1 \UART_2:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_state_0\/main_8 75.626 MHz 13.223 28.444
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_state_0\/main_8 5.666
macrocell8 U(0,0) 1 \UART_2:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_state_2\/main_8 75.626 MHz 13.223 28.444
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_state_2\/main_8 5.666
macrocell9 U(0,0) 1 \UART_2:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_status_3\/main_5 75.660 MHz 13.217 28.450
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_status_3\/main_5 5.660
macrocell12 U(0,0) 1 \UART_2:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_last\/main_0 75.809 MHz 13.191 28.476
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_last\/main_0 5.634
macrocell6 U(1,0) 1 \UART_2:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\UART_2:BUART:rx_last\/q \UART_2:BUART:rx_state_2\/main_9 3.477
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 \UART_2:BUART:rx_last\ \UART_2:BUART:rx_last\/clock_0 \UART_2:BUART:rx_last\/q 1.250
Route 1 \UART_2:BUART:rx_last\ \UART_2:BUART:rx_last\/q \UART_2:BUART:rx_state_2\/main_9 2.227
macrocell9 U(0,0) 1 \UART_2:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_bitclk_enable\/q \UART_2:BUART:sRX:RxShifter:u0\/cs_addr_0 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,1) 1 \UART_2:BUART:rx_bitclk_enable\ \UART_2:BUART:rx_bitclk_enable\/clock_0 \UART_2:BUART:rx_bitclk_enable\/q 1.250
Route 1 \UART_2:BUART:rx_bitclk_enable\ \UART_2:BUART:rx_bitclk_enable\/q \UART_2:BUART:sRX:RxShifter:u0\/cs_addr_0 2.302
datapathcell1 U(1,1) 1 \UART_2:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_status_3\/q \UART_2:BUART:sRX:RxSts\/status_3 3.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,0) 1 \UART_2:BUART:rx_status_3\ \UART_2:BUART:rx_status_3\/clock_0 \UART_2:BUART:rx_status_3\/q 1.250
Route 1 \UART_2:BUART:rx_status_3\ \UART_2:BUART:rx_status_3\/q \UART_2:BUART:sRX:RxSts\/status_3 4.343
statusicell1 U(1,1) 1 \UART_2:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_load_fifo\/main_4 3.783
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,0) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/clock_0 \UART_2:BUART:rx_state_2\/q 1.250
Route 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_load_fifo\/main_4 2.533
macrocell7 U(0,0) 1 \UART_2:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_stop1_reg\/main_3 3.783
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,0) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/clock_0 \UART_2:BUART:rx_state_2\/q 1.250
Route 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_stop1_reg\/main_3 2.533
macrocell11 U(0,0) 1 \UART_2:BUART:rx_state_stop1_reg\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_status_3\/main_4 3.783
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,0) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/clock_0 \UART_2:BUART:rx_state_2\/q 1.250
Route 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_status_3\/main_4 2.533
macrocell12 U(0,0) 1 \UART_2:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_0\/main_4 3.784
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,0) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/clock_0 \UART_2:BUART:rx_state_2\/q 1.250
Route 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_0\/main_4 2.534
macrocell8 U(0,0) 1 \UART_2:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_2\/main_4 3.784
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,0) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/clock_0 \UART_2:BUART:rx_state_2\/q 1.250
macrocell9 U(0,0) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_2\/main_4 2.534
macrocell9 U(0,0) 1 \UART_2:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_3\/main_4 3.784
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,0) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/clock_0 \UART_2:BUART:rx_state_2\/q 1.250
Route 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_state_3\/main_4 2.534
macrocell10 U(0,0) 1 \UART_2:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_state_3\/q \UART_2:BUART:rx_state_0\/main_3 3.949
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,0) 1 \UART_2:BUART:rx_state_3\ \UART_2:BUART:rx_state_3\/clock_0 \UART_2:BUART:rx_state_3\/q 1.250
Route 1 \UART_2:BUART:rx_state_3\ \UART_2:BUART:rx_state_3\/q \UART_2:BUART:rx_state_0\/main_3 2.699
macrocell8 U(0,0) 1 \UART_2:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_2:BUART:rx_last\/main_0 8.374
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_last\/main_0 5.634
macrocell6 U(1,0) 1 \UART_2:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_status_3\/main_5 8.400
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_status_3\/main_5 5.660
macrocell12 U(0,0) 1 \UART_2:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_state_0\/main_8 8.406
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_state_0\/main_8 5.666
macrocell8 U(0,0) 1 \UART_2:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:rx_state_2\/main_8 8.406
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:rx_state_2\/main_8 5.666
macrocell9 U(0,0) 1 \UART_2:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_2:BUART:sRX:RxShifter:u0\/route_si 9.251
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_341 Rx_1(0)/fb \UART_2:BUART:sRX:RxShifter:u0\/route_si 6.511
datapathcell1 U(1,1) 1 \UART_2:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
\UART_2:BUART:txn\/q Tx_1(0)_PAD 31.332
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,1) 1 \UART_2:BUART:txn\ \UART_2:BUART:txn\/clock_0 \UART_2:BUART:txn\/q 1.250
Route 1 \UART_2:BUART:txn\ \UART_2:BUART:txn\/q Net_336/main_0 4.483
macrocell1 U(1,0) 1 Net_336 Net_336/main_0 Net_336/q 3.350
Route 1 Net_336 Net_336/q Tx_1(0)/pin_input 5.769
iocell3 P1[5] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.480
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000